Lecture 13

Data-Level Parallelism

Lecture

Slides (PDF, PPTX).

Outline:

TODO

Workshop

Outline

• Using RISC-V 64-bit instructions to simulate vector operations

Examples

• add_vector.s

NOTE: The ld and sd instructions are 64-bit load and store correspondingly. They are available in the 64-bit version of RISC-V and 64-bit mode of RARS. To enable 64-bit mode in RARS, tick the checkbox in the Setting | 64-bit menu item. This will make all general-purpose registers 64-bit wide. The ld and sd instructions work in the same way as lw and sw, the only difference is the data size that becomes 64 bits (or 8 bytes). See the “Chapter 7. RV64I Base Integer Instruction Set” in the RISC-V instruction set manual for details.

Tasks

• Write a program that inputs an integer value N, inputs 2 matrices of size 4 * N, adds the two matrices, and prints the resulting matrix. Each element of a matrix is a byte value. Elements of the matrices are added by 4, to simulate vector operations. Hint: Use the lw and sw instructions to load and store 4 elements at once.

Homework

TODO

References

• Programming with RISC-V Vector Instructions