Computer Architecture Test (2026)
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What is stored in a compiled program (executable file)?
A. Local variables B. Global variables C. Literals (constants) D. Instructions E. Dynamic variables
Answer: B, C, D
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What data types will have different sizes in 32-bit and 64-bit machines?
A.
charB.shortC.intD.longE.floatF.doubleG.void *Answer: D and G
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You have a data struture with the following fields:
char a; short b; unsigned char c; int d;. What is its size in bytes (taking into account aligment)?Answer: 12
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What is the lowest possible value for a 5-bit signed integer (write it in binary format
xxxxxx)?Answer: 10000
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64-bit value
0xDEADBEEFBAADF00Dis stored in memory of a Little-Endian machine at address0x0. How its bytes are placed into memory (from0x0to0x7)?A.
0xde, 0xad, 0xbe, 0xef, 0xba, 0xad, 0xf0, 0x0dB.0x0d, 0xf0, 0xad, 0xba, 0xef, 0xbe, 0xad, 0xdeC.0xdo, 0xof, 0xda, 0xab, 0xfe, 0xeb, 0xda, 0xedAnswer: B
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The value of signed 16-bit variable
xis0x8000(hexadecimal). What is the value of-x(decimal)?Answer: -32768
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Which bit trick can be used to check whether the value of
xis a power of two?A.
x & (x + 1)B.x & (x - 1)C.x | (x + 1)D.x | (x - 1)Answer: B
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We have a signed 4-bit integer data type. What expressions will result in an integer overflow?
A.
5 + 3B.5 - 3C.-5 + 3D.-5 - 3Answer: A
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This is a 32-bit floating-point value written in binary format:
11000000011100000000000000000000. What is the decimal value for this binary representation?Answer: -3.75
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What RISC-V instruction can read the current value of the program counter (PC)? Write its name in CAPSLOCK.
Answer: AUIPC
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Here are 4 RISC-V instructions in hexadecimal encoding. Which of them have the same opcode?
A.
0x00000303B.0x00000293C.0x00002023D.0x00002283Answer: A and D
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The following RISC-V program has a bug. What register does function
Aneed to save before calling functionBand to restore after to fix the problem? Type its name in small letters.main: addi a0, zero, 10 jal A li a7, 1 ecall li a7, 10 ecall A: addi a0, a0, 5 jal B addi t1, zero, 1 add a0, a0, t1 ret B: addi t0, zero, 100 mul a0, a0, t0 retAnswer: ra
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What type pipeline hazards can be avoided by using separate instruction and data caches?
A. Control hazard B. Data hazard C. Structural hazard D. Memory hazard
Answer: C
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How many clock cycles its takes to execute the following instuction sequence? We have a classical 5-stage pipeline that supports forwarding?
lw x1, 0(x0) lw x2, 8(x0) add x3, x1, x2 addi x3, x3, 10 sw x3, 24(x0) lw x4, 16(x0) add x5, x1, x4 sw x5, 32(x0)Answer: 14
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What is the typical size (in bits) of virtual address in modern 64-bit Intel processors?
Answer: 48
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We have a 32-bit address and a 2-way accosiative cache that contains 128 entries with block size of 64 bytes. What it the tag size in bits?
Answer: 20
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How many instances of L3 caches does a 24-core Intel Core i7 have?
Answer: 1
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How many hardware threads per core does Intel Core i7 support?
Answer: 2
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What type of parralelism implemented in modern CPU does NOT require assistance of a programmer?
A. Instruction-level parallelism B. Data-level parallelism C. Thread-level parallelism
Answer: A
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How many 32-bit integer values can be added simultaneously using Intel’s AVX2 SIMD instructions.
Answer: 8